An electrostatic discharge (ESD) event refers to a temporary and abrupt flow of current between two objects of differing electrical potentials. ESD can be a serious issue for an integrated circuit device (IC), as large potential changes and current flows that occur during the ESD event can damage silicon junctions and oxide insulators. Damage to an IC from the ESD event can diminish the performance of the silicon-based IC, if not render the IC inoperable.
A buildup of charge on an IC may occur for a variety of different reasons, many of which occur during the manufacturing, assembly, testing, or use of the IC. As a result, an IC may be subjected to inadvertent ESD events prior, and subsequent, to assembly and sale. ESD protection schemes are implemented to protect devices internal to the IC which may be vulnerable to ESD events. These vulnerable devices are typically devices that output to, or come in contact with, external nodes of the IC. ESD protection schemes, when enabled during the ESD event, provide alternative current pathways for large currents generated during the ESD event. These alternative pathways attempt to steer current around vulnerable devices, effectively bypassing the ESD sensitive sections of the IC.
When a metal oxide semiconductor field effect transistor (MOSFET) device is used as an output driver, a drain terminal of the MOSFET device is coupled to an output pad. In this configuration, the MOSFET device is exposed to the external environment via the output pad. Such exposure makes the MOSFET device vulnerable to ESD events. One approach to protecting a MOSFET device from ESD events takes advantage of a parasitic bipolar junction transistor inherent in the structure of the MOSFET device. For example, within the structure of an N-type MOSFET (NFET) device resides a parasitic N-P-N bipolar junction transistor (parasitic BJT). Typically, the parasitic BJT is not a highly effective device and, as such, does not function during normal operation of the NFET device. However, the high voltage potentials generated during an ESD event can initiate a snapback mode in the NFET device, thereby enabling the parasitic BJT. When the NFET operates in snapback mode, the parasitic BJT has a high current carrying capacity and can safely bypass current generated by the ESD event through the NFET device structure. When properly sized, the parasitic BJT can provide ESD protection to the NFET device without degrading the intended functionality of the NFET device.